In CMOS technology both p- and n-channel transistors are used. When an enhancement mode n-channel MOS transistor is connected in a series common-gate configuration with an enhancement mode p-channel MOS transistor, the resulting structure functions as a simple inverter and dissipates virtually no power whatsoever so long as the inverter is in one of its two stable states. In either of the two stable conditions, one of the transistors will be in a very high impedance OFF state, consequently, the series combination of the two devices will draw almost no steady-state current. Power will only be dissipated during switching from one state to the other. For this reason CMOS has become, in recent years, an important semiconductor technology which allows more circuits within the power constraints of a given package. Compared to bipolar or even NMOS, the greater number of circuits permitted within the package and the resulting reduction in package interfaces can be used by system architects to achieve better system performance. CMOS can also reduce system cost by eliminating the need for cooling fans and reducing the size of power supplies. The major shortcomings of this technology have been the more complex processing, the increased layout area requirement and the possibility of latchup.
In bulk CMOS both n-channel and p-channel transistors are typically formed, as shown in FIG. 1, and designated by the numerals 1 and 2, respectively. The n-type silicon wafer substrate 3, has a p-type well 4 therein, created by diffusion or ion implantation of dopant impurities. An n-channel transistor is created by ion implantation of an n.sup.+ source element 5 and an n.sup.+ drain element 6 within the p-well region, and the deposition of a thin gate oxide layer 7 and a heavily-doped gate layer 8. The p-channel transistor is made by ion implantation of a p.sup.+ source 9 and a p.sup.+ drain 10 in the n-substrate and the deposition of a thin gate oxide layer 11 and a heavily-doped gate layer 12.
CMOS process technology is undergoing extensive experimentation in processing steps and parameters in order to provide a process architecture which is latch-up free and achieves a maximum layout density with a simple process comprising fewer low complexity processing steps. Today's drive toward smaller device geometries has exascerbated the latchup problem inherent in the bulk CMOS devices. During latchup, the presence of a four layer pnpn structure (elements 9/3/4/6 in FIG. 1), causes a near short circuit condition across the power supply. If current flow is not limited by external means, such as guard rings, some metal or diffusion current paths will blow open. Guard rings are low resistivity connections to supply voltages built around the CMOS p-channel and n-channel transistors. They have the effect of protecting againast latch-up but reduce the gate density by requiring more space between the n- and p-channel transistors. Another alternative for reducing the latch-up phenomenon is to increase the distance between the p-well and p-diffusion, effectively increasing the width of the base region for pnp transistors. Here again, some area is wasted, reducing the gate density. In bulk CMOS the chance of latchup can be reduced only at the expense of silicon areas or the addition of a more expensive epitaxial layer.
The basic design challenge has been to fabricate both p-channel and n-channel transistors on the same wafer, to optimize their performance, and to maximize their density. One relatively simple approach has been SOS (silicon-on-sapphire) CMOS, illustrated in FIG. 2 in which the n-channel transistor 13 and the p-channel transistor 14 are formed on top of the substrate 15. The sapphire (aluminum oxide) wafer's crystal lattice is compatible with that of the silicon grown thereon. Rather than diffusing wells and n- and p-type regions within the substrate, a p-type silicon island 16 and an n-type silicon island 17 are patterned on top of the substrate and are then properly doped for transistor action. The p-type island 16 receives n-type dopant to form an n-channel device and the n-type island 17 receives p-type dopant to form a p-channel device. A gate oxide layer 18 and a suitably doped semiconductor gate layer 19 are deposited upon the islands. An advantage of this approach is the inherent isolation of the transistors and the possibility of increased device density by scaling. A disadvantage of the SOS process is that the dielectric constant of sapphire is high compared with that of silicon. This results in a higher coupling capacitance in the adjacent wires, which gets worse with scaling, and affects speed adversely.
In both of the above-described processes, doping is accomplished by ion implantation which, for all practical purposes, presents a size limitation for the substrate. This is because ion implantation equipment for large area (e.g. on the order of about 10.times.12 inches) processing is not commercially available today.
It is an object of the present invention to provide a thin film SOI CMOS device wherein the suitably doped deposited layers of an n-channel transistor and its complementary p-channel transistor are simultaneously deposited.
It is also an object of our invention to provide a simplified process for fabricating CMOS devices on large area substrates with simultaneously deposited source and drain layers which are in-situ doped with appropriate dopants.
It is another object of our invention to provide a simplified process for fabricating a thin film SOI CMOS device wherein the p- and n-channel transistors are inherently isolated so as to eliminate latch-up, and scaling can be achieved for maximizing device density.
It is a further object of our invention to provide a self-aligned thin film SOI CMOS device.